A multilevel NAND flash memory where each of the memory cells can hold two or more bits of data has been known. It is known that flag data indicating how many pages of memory cells have been written (e.g., indicating data has been written only up to the lower page or already up to the upper page) is used in a multilevel NAND flash memory. Such a technique has been disclosed in, for example, Japanese Patent No. 3935139. When data is read, the flag data is checked in advance, which enables a proper read operation.
However, the conventional method requires time to check the flag data. This might prevent the NAND flash memory from operating at higher speed or make the circuit size larger.